Exponential growth in every industry eventually has to come to an end, according Anderson, who cited railroads and speed increases in the aircraft industry, the report said.

“A generation or two of continued exponential growth will likely continue only for leading-edge chips such as multicore microprocessors, but more designers are finding that everyday applications do not require the latest physical designs,” Anderson said in the EE Times’ report. Anderson also cited the staggering costs of research and fabs (factories) as a formidable barrier for continued advancement. Few companies can afford chip plants that typically cost billions of dollars to build and maintain.

So, what does the future hold? Anderson cited three technologies: optical interconnects, 3D chips–which have circuits and components stacked on top of each other–and accelerator-based processing as seeing significant advancements, the report said. The latter technology, accelerators, is hot right now.

In addition to IBM, companies such as Nvidia and Advanced Micro Devices’ ATI unit supply graphics-processor-based computers to accelerate scientific, engineering, and animation applications. Intel is also expected to bring out its Larrabee chip later this year or early next year that can be used as an accelerator.

Brooke Crothers is a former editor at large at CNET News.com, and has been an editor for the Asian weekly version of the Wall Street Journal. He writes for the CNET Blog Network, and is not a current employee of CNET. Contact him at mbcrothers@gmail.com. Disclosure.

Although the chip has a fraction of the number of neurons or connections found in a brain, its design allows it to be scaled up, says Karlheinz Meier, a physicist at Heidelberg University, in Germany, who has coordinated the Fast Analog Computing with Emergent Transient States project, or FACETS.

The hope is that recreating the structure of the brain in computer form may help to further our understanding of how to develop massively parallel, powerful new computers, says Meier.

This is not the first time someone has tried to recreate the workings of the brain. One effort called the Blue Brain project, run by Henry Markram at the Ecole Polytechnique Fédérale de Lausanne, in Switzerland, has been using vast databases of biological data recorded by neurologists to create a hugely complex and realistic simulation of the brain on an IBM supercomputer.

FACETS has been tapping into the same databases. “But rather than simulating neurons,” says Karlheinz, “we are building them.” Using a standard eight-inch silicon wafer, the researchers recreate the neurons and synapses as circuits of transistors and capacitors, designed to produce the same sort of electrical activity as their biological counterparts.

A neuron circuit typically consists of about 100 components, while a synapse requires only about 20. However, because there are so much more of them, the synapses take up most of the space on the wafer, says Karlheinz.

The advantage of this hardwired approach, as opposed to a simulation, Karlheinz continues, is that it allows researchers to recreate the brain-like structure in a way that is truly parallel. Getting simulations to run in real time requires huge amounts of computing power. Plus, physical models are able to run much faster and are more scalable. In fact, the current prototype can operate about 100,000 times faster than a real human brain. “We can simulate a day in a second,” says Karlheinz.

While it may sound implausible, neurons are actually very slow, at least compared to computers, says Thomas Serre, a computational neuroscience researcher at MIT. “The reason why computers seem much slower is that they are serial machines, while our brains run in parallel,” he says.

FACETS is not the only group taking this approach. Researchers at Stanford University have also been creating neuronal circuits and the Defense Advanced Research Projects Agency recently started funding a similar project.

“Where FACETS is ahead of anybody else is that they use these complex synapses,” says Markram. While the neurons are quite simple, he says, the synapses are designed to use a very powerful distributed algorithm–developed by Markram–called spike-timing dependent plasticity, that allows the device to learn and adapt to new situations.

Building such complex circuits has required close collaboration with neurobiologists, says Markram. In fact, the project, whose current budget is €10.5 million (US$14.1 million), relies upon the contributions of 15 scientific groups from seven different countries. Among the challenges they face is recreating the three-dimensional structure of the brain in a 2-D piece of silicon, he says.

Despite efforts to make the chips as biologically plausible as possible, Markram admits they are still crude compared to what can be achieved in simulation. “It’s not a brain. It’s a more of a computer processor that has some of the accelerated parallel computing that the brain has,” he says.

Because of this, Markram doubts that the hardware approach will offer much insight into how the brain works. For example, unlike Blue Brain, researchers won’t be able to perform “in silico” drug testing, simulating the effects of drugs on the brain. “It’s more a platform for artificial intelligence than understanding biology,” he says.

The FACETS group now plans to further scale up their chips, connecting a number of wafers to create a superchip with a total of a billion neurons and 1013 synapses.

Source: http://www.technologyreview.com/computing/22339/

The pitch goes like this: “Learn how to easily add real-time 3D smoke, fog and other fluid simulations to your game without using up the GPU.” That’s according to an Intel Web page entitled Intel at Game Developers Conference. (The CPU is the central processing unit, or main brains of a computer; GPU stands for graphics processing unit.)

The session abstract goes on to say that the “source code to a fluid simulator optimized for multi-core CPUs…can easily be integrated by game developers into their engines to produce unique 3D effects.”

Intel’s argument raises the question, how should the CPU and GPU divvy up their tasks? In games, the CPU can handle things like physics and AI (artificial intelligence), and certain older games actually run some graphics on the CPU. Generally, however, the GPU is much more efficient (that is, faster) at handling most of the high-end effects that the gamer sees on the screen.

But there are exceptions. “Not all algorithms and processes map well to a GPU,” said Jon Peddie, president of Jon Peddie Research. “You have to have a problem that is naturally parallel, and except for the rendering of, say, a water surface and subsurface and reflections, the wave motion equations will run just fine on a CPU,” Peddie said.

Intel may also be seeking ways to make better use of its quad-core processors, according to Tom R. Halfhill, an analyst at the Microprocessor Report. But, he added: “I need to be convinced that a CPU can do those 3D effects better than a GPU can.”

Then, there’s also the Larrabee factor. Larrabee is an upcoming high-end graphics processor due late this year. “I’m sure some of it may also relate to Larrabee, which will include x86 cores, if or when it comes to market,” said Jim McGregor, an analyst at In-Stat.

(This Mythbusters demonstration at an Nvidia conference is oversimplified and self-serving but it crystallizes the difference between CPUs and GPUs.)

In another GDC session, Intel is also pushing the CPU for physics and AI: “How can your game have more accurate physics, smarter AI, more particles, and/or a faster frame-rate? By threading your game’s engine to take advantage of multi-core processors. Intel has built a threaded game engine and demo called ‘Smoke’ that shows one way of achieving this goal,” the abstract states.

It continues: “This presentation examines the Smoke architecture and how it is designed to take advantage of all CPU cores available within a system. It does this by executing different functional and data blocks in parallel to utilize all available cores.”

Intel won’t stop there. It will also focus on the bane of many PC game developers: gaming on Intel integrated graphics silicon–a relatively low-performance platform that prohibits game titles from being displayed in all their glory at higher resolutions. The session will focus on “programming for scalable graphics applications” and cover “performance considerations when programming for integrated graphics in general with specific tips for Intel Integrated graphics.”

source:
Brooke Crothers is a former editor at large at CNET News.com, and has been an editor for the Asian weekly version of the Wall Street Journal. He writes for the CNET Blog Network, and is not a current employee of CNET. Contact him at mbcrothers@gmail.com. Disclosure.

The high-throughput method they promote can also use other ubiquitous technologies like IBM’s Cell Broadband Engine processor (included in Sony’s Playstation 3) or Amazon’s Elastic Cloud Computing services.

Interestingly, the team is also involved in the PetaVision project on the Roadrunner, the world’s fastest supercomputer

http://hardware.slashdot.org/article.pl?no_d2=1&sid=08/07/27/0721222

The IBM documents have the eight-core Power7 being arranged in dual-chip modules. So, that’s 16-cores per module. As IBM tells it, each core will show 32 gigaflops of performance, bringing each chip to 256 gigaflops. Just on the gigaflop basis, that makes Power7 twice as fast per core as today’s dual-core Power6 chips, although the actual clock rate on the Power7 chips should be well below the 5.0GHz Power6 speed demon.

In fact, according to our documents, IBM will ship Power7 at 4.0GHz in 2010 on a 45nm process. We’re also seeing four threads per core on the chip.

For some customers, IBM looks set to create 2U systems with four of the dual-chip modules, giving the server 64 cores of fun. These 2U systems will support up to 128GB of memory and hit 2 teraflops.

IBM has an architecture that will let supercomputing types combine these 2U boxes to form a massive unit with 1,024 cores, hitting 32 teraflops of performance with 2TB of memory.

And, er, if you are a seriously demanding type, boy, does IBM have the system for you.

The Giant
The Register has uncovered the first detailed specifications of the “Blue Waters” system IBM is building for the National Center for Supercomputing Applications (NCSA).

If our documents are to be believed – and they’re penned by an IBM executive – this system, funded by a $208m grant and meant to go up at the University of Illinois in 2011, will be the most massive machine ever created.

We’ve got documents showing IBM going after a 10 petaflop system (peak) comprised of 38,900 eight-core Power7 chips with each chip running at 4.0GHz. This monster will have an astonishing 620TB of memory and 5PB/s of memory bandwidth.

According to the documents, IBM will rely on a 1.30PB/s interconnect to link the systems and will feed them with 26PB of storage. As if that’s not enough, IBM will offer an exabyte of archival storage. Why not?

This insane machine will be built out of more than 100 racks filled with servers and storage systems, taking up close to 4,400 sq. feet.

Er, if this stuff isn’t sending shivers down the spines of Sun and Intel, then I don’t know what will.

IBM has clearly decided to get a bit radical with Power7. This isn’t the single-thread focused Power6. It’s a true multi-core chip, which should stack up very, very well against Sun’s 16-core rock and what will likely be an eight-core version of Itanium around in 2010.

And then IBM still has the Quasar project lurking in the background, where it’s combining Power and Cell chips. Stand back, friends. Stand back. ®

High-performance computing (HPC) applications are likely to see several new technologies this week. In the hardware arena, AMD already announced its 1+ TFlop GPU earlier today and Nvidia is following with a GT200 based GPGPU, also claiming to be capable of hitting 1 TFlop per processing unit in single precision applications. Compared to the first generation, the floating point performance is up from 518 GFlops.

The new T10P processing unit represents a massive die, integrating 1.4 billion transistors and 240 processing cores, which is up from 128 cores in the 8-series of GPUs.

Nvidia has cut the deskside supercomputer (D870), answering to trends of customers who have been purchasing workstation graphics cards rather than an expensive external add-on, and is now limiting the product portfolio to a 4-GPU 1U blade and a Tesla add-in card. The S1070 blade integrates GPUs clocked at 1.5 GHz, a total of 960 processing cores, 4 GB of GDDR3 800 memory per GPU for a 16 GB total, 408 GB/s memory bandwidth and a total processing capability of 4 TFlops. Power consumption is up from 550 watts in the first generation to 700 watts

The blade will be offered with either 2 PCIe interfaces ($7995) or one PCIe connect ($8295), both of which are slightly more expensive than the S870 blade, which sold for $7500 at introduction.

The entry-level Tesla product remains an add-in card, in this case the C1060, which essentially represents Quadro graphics card on steroids. The card includes on T10P processor, 102 GB/s memory bandwidth and a power consumption rating of 160 watts, down from 170 watts of the previous generation. Nvidia said that thermal restrictions forced the company to clock the C1060 GPUs at 1.33 GHz instead of the 1.5 GHz in the blade. As a result, the C1060 will not hit 1 TFlops and is estimated to check in at about 900 GFlops.

The C1060 will be offered for $1699 MSRP, up from the $1500 price tag of the original C870.

Besides performance improvements, the T10P also delivers 64-bit or double-precision capability, which is required for most fluid dynamics and financial stream processing applications. Double precision is substantially more intensive than single precision calculations and with decrease the performance of the card dramatically. Nvidia told us that double-precision calculations will result in a 90% speed penalty and deliver only 100 GFlops per T10P processor.

There is also news surrounding the CUDA application platform, which Nvidia says can be used more any multi-core processing environment out there: This summer, the company will release a beta version of CUDA that developers can apply to multi-core CPUs. Nvidia claims that CUDA has been downloaded 60,000 times so far, but it is safe to say that there aren’t 60,000 developers working on HPC applications – and even Nvidia admits that most of those 60,000 developers are “playing” with CUDA trying to create “consumer applications.” The expansion into the CPU area could help the company reach a far greater developer base than it is able to attract with a GPU-only software foundation.

Technically, there is nothing that prevents from CUDA to also be used for ATI’s GPU products, Nvidia told us. However, not surprisingly, Nvidia said that it won’t be offering CUDA for ATI products and stated that “someone else can do that.” ATI offers its own high-level development tools called Brook+.

Source:

http://www.tgdaily.com/html_tmp/content-view-37955-135.html

The idea here is that Cell will be a commodity processor (at least that’s what the authors and IBM hope), so it’ll be a viable HPC alternative for the cost-sensitive academic research market. This paper represents the first formal academic attempt to decide if Cell hardware is something that researchers will want to invest in.

So how does Cell stack up in comparison to these three competitors? In a word, it screams.

First, the good news
Take a look at the following results for single-precision dense matrix multiplication, or GEMM (all numbers are Gflop/s):

Cellpm: 204.7
Cray X1E: 29.5
AMD64 7.8:
Itanium2: 3.0

The “pm” above means “performance model.” Because Cell hardware isn’t generally available for tests like this, the paper’s authors used a combination of performance projections and benchmarks on a cycle-accurate simulation of Cell that IBM has released. Real-world results should be very comparable to those in the paper, if not even better.

Note that the above results aren’t exactly typical. In some of the rest of the tests, Cell is only a mere ten times faster than the competition. Also, I should mention that the paper also looks into power consumption, and Cell still manages to trounce the other guys at performance/watt.

Needless to say, these results are extremely promising, and the authors of the paper clearly believe that Cell could change the HPC game if it is available in quantity and at commodity prices. I personally think that Cell’s “commodity” status outside of the PS3 is a bigger “if” than the paper presumes, but we’ll see soon enough.

Now for the caveats
So now that we’ve seen that Cell blows away the competition for these HPC kernels, that means that it’s going to completely dominate the next-gen console market and kill Itanium, right? Not exactly.

First, single-precision (SP) is the place where Cell really blows the doors off the barn, because SP is what game developers need. IBM made some compromises on double-precision (DP) performance, with the result that such performance is a fraction of what it is for SP. On DP code, Cell merely leads the pack for most of the tests.

The paper’s authors propose a microarchitectural improvement to Cell’s DP capabilities that they call Cell+, and they’re clearly hoping IBM will adopt their suggestion. Cell+ significantly enhances DP throughput with minimal changes, so we’ll see if IBM bites.

Another thing that should be pointed out is that the Cell used in the paper has full access to all eight SPEs, and not the six SPEs of the PS3. (Remember, one SPE is disabled for yield reasons, and the other is reserved for the system.) So keep this in mind when fantasizing about how these results are going to extrapolate to the PS3 hardware.

More important than the eight vs. six SPE issue is the fact that, due to the nature of the kernels used and the way that they were implemented for these tests, taking these results and trying to think about how a future iteration of Gran Turismo will look on the PS3 is a bit like comparing apples to cucumbers. Here’s why.

Programming models and the big picture
To get the kinds of mind-blowing results found in the paper, the Berkeley team took each kernel and custom-fit it to the bare Cell hardware using labor-intensive intrinsics and extensive hand optimization. They didn’t rely on IBM’s higher-level development tools, and they didn’t even code the kernels in C. In other words, they were operating at “Tier I” of the Cell programming complexity hierarchy. By taking into account things like the deterministic load latencies at the various levels of the memory hierarchy, this code was tuned and timed, cycle by cycle and word by word, to fit the cell hardware.

Our first Cell implementation, SpMV, required about a month of learning the programming model, the architecture, the compiler, the tools, and deciding on a final algorithmic strategy. The final implementation required about 600 lines of code. The next code development examined two flavors of double precision stencil-based algorithms. These implementations required one week of work and are each about 250 lines, with an additional 200 lines of common code. The programming overhead of these kernels on Cell required significantly more effort than the scalar version’s 15 lines, due mainly to loop unrolling and intrinsics use. Although the stencils are a simpler kernel, the SpMV learning experience accelerated the coding process.

Having become experienced Cell programmers, the single precision time skewed stencil — although virtually a complete rewrite from the double precision single step version — required only a single day to code, debug, benchmark, and attain spectacular results of over 65 Gflop/s. This implementation consists of about 450 lines, due once again to unrolling and the heavy use of intrinsics.

The authors were able to do this kind of custom fit because they picked a programming model based on data parallelism. What this means is that they had the eight SPEs doing identical work on different parts of a highly parallel dataset. When you’ve got all eight SPEs marching in lock-step through a large, parallel dataset, then you can really put all of the hardware on that chip to work in a dramatic way, as the paper indeed shows.

IBM, however, is pushing a task-based approach to parallel programming the Cell, where there are many individual tasks running concurrently on the different SPEs. This is way harder to code for and optimize than the data parallism-based approach used in the paper, but it’s also where the money’s at in the consumer and game markets.

In the end, what the paper demonstrates is that, for the HPC kernels that are amenable to a data parallelism programming model, then Cell’s particular combination of a software-controlled memory hierarchy (with deterministic load latencies) and an obscene amount of parallel execution hardware is clearly the way to go. This approach is dramatically superior to a general-purpose computing architecture with a hardware-controlled memory hierarchy from both performance and performance/watt perspectives.

If Cell doesn’t really catch on as a commodity part outside the PS3, I expect we’ll eventually be posting a news item about a lab somewhere (Iran?) that placed an order for 200 PS3 consoles, with plans to cluster them.

Speaking of the PS3, that’s going to feature mostly task-based programming, which as I just said is a different beast than what was done in the Berkeley paper. Also, the programming will be done at higher levels of abstraction from the hardware. So please, don’t read this and then assume that Cell will administer a similar drubbing to general-purpose architectures like Opteron, Itanium, and Conroe on all game, physics, and AI code.

Source:

http://arstechnica.com/news.ars/post/20060615-7071.html

If you haven’t already, I would HIGHLY recommend you look over my original terascale computing article, as it covers the basics of how such an architecture functions and the benefits and drawbacks it offers for computing. In fact, the product that is being showcased with Intel’s announcement today is basically the same thing we saw at IDF last year; onlnow we are getting data on frequencies and computing horsepower that were left out before.

I will be including the terascale backup data (the general information that leads up to today’s announcement) after the new information is shown here; so look for the remainder of the article should you need more information.

An 80-tile 1.28 TFLOPS CPU

Yes, we are indeed looking at what is essentially an 80-core processor; one of the world’s first and probably most exciting. The basic architecture of the 80-tile design is based on the ideas of a NoC architecture, or Network-on-Chip, that contains hundreds of processing elements with integrated on-die communications. The tiles are arranged in a 10×8 2D mesh and can operate at speeds up to 4 GHz.

Each of these 80-tiles consist of a processing engine connected to a 5-port router for passing data amongst the tiles with a bandwidth up to 256GB/s. On each tile’s processing engine (PE) there are two floating point units that are single precision. For data storage, the PE includes a 3KB instruction memory and a 2KB data memory.

Each of the FPMACs (floating point units) has a 9-stage pipeline that can reach a sustained multiply-add result (2FLOPS) every cycle. With dual FPMACs in each PE, the tile can provide 16GFLOPS of aggregate performance at the peak 4 GHz clock speed.

The chips clocking scheme allows for mesochronous timing to allow for communication between the tiles independent of the clock timings. The PLL (PLL: Wikipedia) responsible for the clocks runs on both the horizontal and vertical axis (called spines) and distributes the clock information in timing pattern shown on the right hand side.

One of the most interesting parts of this chips design is the amount of power control that has gone into it. Fine-grained clock gating, sleep transistor cycles and enhanced circuits all combine to reduce the power the chip uses all in the hardware itself. In fact, each of the 80 tiles has 21 smaller sleep-sections that can be activated separately and the tiles use a 6-cycle pipeline wakeup sequence.

This sleep cycle method serves purposes: 1) it mitigates the current spikes that might arise from 80 cores waking up simultaneously and 2) it allows the FPMAC execution (data processing) to start only a single cycle into that wakeup sequence. Essentially, each tile can begin processing data before the rest of it wakes up. In all, about 90% of the FPMAC transistors and 74% of the total of each PE is sleep-enabled.

Even more impressive, this chip is able to achieve incredibly high clock speeds on modest power usage. Running on a 1.0v current at 110 degrees C the tile maximum frequency is 3.13 GHz while at 1.2v the tiles can run at 4.0 GHz. That brings the peak processing performance with all 80 tiles functioning on block matrix operations to 1.0TFLOPS at 1.0v and 1.28TFLOPS at 1.2v. Power consumption at these levels is estimated at 98W and 181W respectively.

Finally, we have a layout of the chip itself that measures only 275mm^2 in area; that is 3mm^2 for each tile with some additional I/O area added in. Built on a 65nm process technology and using standard copper interconnects, this chip is designed with a unique 1248-pin LGA package design and uses 100 million transistors.

No-where-near-closing Thoughts

This information that reached my inbox tonight is revolutionary beyond what I expected to see after being introduced to the technology late last year.

Here is a direct quote from the Intel PR:

“Intel has no plans to bring this exact chip designed with floating point cores to market. However, the company’s terascale research is instrumental in investigating new innovations in individual or specialized processor or core functions, the types of chip-to-chip and chip-to-computer interconnects required to best move data and, most importantly, how software will need to be designed to best leverage multiple processor cores. This Teraflops research chip offered specific insights in new silicon design methodologies, high-bandwidth interconnects and energy management approaches.”

Again, Intel is adamant about this product NOT being design with any specific purpose in mind, but I think they would be crazy to not further develop this technology into areas that could use the kind of processing power it provides. We’ve already heard talks about Intel going into the discrete GPU business, and our original look at the terascale computing projects looked at how this chip could handle real-time ray tracing. Such applications, as well as all kinds of super-computing algorithms could benefit from TFLOP performance on a single chip.

Here is another quote to get excited about:

“Further Tera-scale research will focus on the addition of 3-D stacked memory to the chip as well as developing more sophisticated research prototypes with many general-purpose Intel® Architecture-based cores. Today, the Intel® Tera-scale Computing Research Program has more than 100 projects underway that explore other architectural, software and system design challenges.”

Adding 3D memory to the terascale processor is a requirement to fill the huge amount of processing power this chip can provide with data to actually perform it on. Also interesting to see is how Intel might be able to apply a more generic x86-like architecture to such a tiled design to bring this kind of power to even more users that demand it.

In all, this new announcement only adds to the allure of such 80-core processors, even with the very specific uses that they might be helpful for in today’s world. As data and storage continue to increase though, the ability to process terabytes of information with teraflops of CPU power is going move from mere theory to reality.

Source

http://www.pcper.com/article.php?aid=363

This new multi-core CPU will bring to the desktop the kind of super computer performance that was available 10 years ago with the exception that the cost will now be dramatically smaller. Obviously, these CPUs will first find their way into server rooms of large data centers but it won’t be long before the cost is lowered and the same technology becomes available to the desktop market. Intel plans to mass produce the new chips in 5 years while its current focus is on bringing to the market their Quad Core CPUs. The latter will become available in November, 2006.

I think that such amazing progress in computing power spells good news for artificial intelligence and robotics. Other than the fact that researchers will now be able to attack larger problems at a much lower cost, many artificial intelligence, computer vision and machine learning algorithms are easily parallelizable and so researchers could easily take advantage of the multiple cores. In addition, Intel is focusing much effort in lowering the power consumption of their new CPUs which can only be good news for robotics. Lower power consumption along with hopefully an increase in battery capacity can lead to robots operating for longer periods of times in excess of the current 1-2 hours. Longer operating times will allow robots to achieve a larger variety of tasks with higher complexity.

I should point out that there is a number of AI researchers that believe that maybe we already have all the computational power that we need in order to achieve human level intelligence but what we luck is the proper methods. They might be correct. However, It is my opinion that having faster computers can help us find these methods since it will now be possible to run more experiments with significantly larger amounts of data.

Source:
http://smart-machines.blogspot.com/2006/09/intel-presents-prototype-cpu-with-80.html